In so called packaging of semiconductor devices it is sometimes required to enclose various components in a controlled atmosphere, i.e. to seal a cavity in a controlled atmosphere, in some cases, even most often to form a hermetic seal. This procedure entails bonding two wafers together often under pressure and with heating. This is a delicate task when wafers are thin because they easily break.
Representative prior art for this field of technology are WO 2007/089206, WO 2008/091220, WO 2008/091221, and SE-0900590-1 (not published) all assigned to Silex Microsystems, and WO 2009/005462 (Nilsson et al). These documents describe various aspects of through silicon insulator technology, such as through silicon vias (TSV), “zero cross-talk” and wafer level micro-scale packaging of discrete or monolithic integrated components.
In US 2004/0259325 (Qing Gan) there is disclosed a wafer level chip scale hermetic seal package. It comprises providing a capping structure having a cavity for housing components on a device substrate, and vias extending through the capping structure for routing electrical signals from the cavity and through the capping. The vias appear to be made by etching holes entirely through the wafer and then filling the vias by electroplating Cu in them. The depth of these vias is said to be limited to 20-300 μm and the cross-sectional dimension 5-50 μm.